The present invention relates to electrical circuits and more particularly to direct current (DC) to direct current (DC) power conversion and regulation.
There is an ever increasing demand for power conversion and regulation circuitry to operate with increased efficiency and reduced power to accommodate the continuous reduction in size of electronic portable devices. Many times these devices are battery powered, and it is desirable to utilize as little power as possible to operate these devices, so that the battery life is extended. Therefore, the prior 5-volt industry standard has decreased to a 3.3 volt industry standard, which may soon be replaced by an even lower standard. Voltage regulators have been implemented as an efficient mechanism for providing a regulated output in power supplies. One such type of regulator is known as a switching regulator or switching power supply, which controls the flow of power to a load by controlling the on and off duty-cycle of one or more power switches coupled to the load. Many different classes of switching regulators exist today. One class of switching regulators is known as non-synchronous buck switching regulators. Non-synchronous buck switching regulators are subject to operating in a discontinuous mode under light or no load conditions. This undesirable result occurs when the current through the inductor is reduced to zero or near zero and then tends to stay at zero or near zero.
FIG. 1 illustrates a conventional switching regulator 10 (e.g., a non-synchronous buck converter). The switching regulator 10 includes a control circuit 12 that is operative to control the duty cycle of pulses provided to a power switch 14 through a driver 16. The control circuit 12 provides a pulse wave signal that is inverted by the driver 16. In the illustration of FIG. 1, the power switch 14 is an N-type MOSFET device. In order to turn on the N-type MOSFET device, the gate must be pulled higher than the source. A capacitor 18, referred to as a bootstrap capacitor or a boot cap, is coupled to the source of the power switch 14 and a diode 20. The diode 20 is also coupled to VIN. The common node of capacitor 18 and the diode 20 is labeled BOOT1 and is also coupled to the supply input of driver 16 and to a resistor 22. The resistor 22 is representative of the load placed on the boot capacitor 18 by one or more level shifters (not shown) of the driver 16. The other end of resistor 22 is coupled to a node labeled PH1, the driver 16, and the source of power switch 14. The node PH1 is also coupled to the capacitor 18, an inductor 24 and a diode 26.
In order to turn on the power switch 14, an N-type MOSFET device, the gate must be pulled higher than the source. When VPH1 is pulled to VIN through power switch 14, VBOOT1 will be pulled to approximately 2*VIN. If VBOOT1 is approximately 2*VIN, then the supply input to driver 16 will be at 2*VIN allowing the output from the driver 16 and the gate of power switch 14 to be pulled higher than the source. When the input to the gate of power switch 14 is high, the source to drain input impedance will be low and the voltage at node PHI (VPH1) will be approximately equal to VIN. When VPH1, is approximately equal to VIN, the inductor current IL1 through inductor 24 will begin to increase. IL1 continues to increase until VPH1, changes.
When the output of the control circuit 12 goes high, the output of driver 16 goes low and the power switch 14 turns off. Since the current IL1 through inductor 24 tends to remain unchanged, VPH1 will be pulled below ground so that current IL1 can be supplied through diode 26. At low loads, IL1 decreases until it reaches approximately zero. When IL1, reaches approximately zero, VPH1 will approximately equal to VOUT1, the voltage across a capacitor 28 and a load resistor 30. The inductor 24 tries to maintain IL1 equal to zero. With IL1, equal to zero and with no source driving node PH1, VPH1 and VOUT1 will ring (fluctuate up and down) until the next switching cycle when the power switch 14 is again turned on.
When IL1 is equal to zero and the ringing described above occurs, the circuit is said to be operating in a discontinuous mode. The current through the inductor 24 is in the form of a triangle wave, increasing when power switch 14 is on and decreasing when power switch 14 is off. This triangle waveform is known as the ripple current. The decreasing portion of the triangle waveform is known as the reverse current. When an adequate minimum load exists, the current through the inductor will not reach zero because the triangle waveform (the ripple current) resides on top of a nominal load current level. However, under light or no load conditions, the inductor current IL1 can reach zero when the negative ramp portion of the triangle reduces to zero. When this occurs, the circuit is said to be operating in the discontinuous mode and the fluctuating voltage (ringing) problems described above will occur.
FIG. 2 is a plot 40 of the voltage at node PHI (VPH1) versus time and a plot 42 of node BOOT1 (VBOOT1) versus time. These plots are merely representative of the type of ringing and voltage fluctuations that can appear on these nodes and are not scale drawings with respect to frequency or amplitude. The scale has been altered to illustrate the problems herein discussed. Looking first to the plot 42, it can be seen that at T1 the voltage VPH1 is approximately equal to VIN when power switch 14 is turned on. At T2, power switch 14 turns off. Since IL1 tends to remain unchanged, VPH1 is initially pulled below ground as diode 26 supplies IL1. IL1 decreases until reaching zero and after initially being pulled below ground, VPH1, begins to ring and fluctuate above and below VIN until T3, when power switch 14 is again turned on and pulls VPH1, to VIN.
At the same time, VBOOT1 exhibits similar behavior. At T2, when power switch 14 is turned off, VBOOT1 rings and fluctuates in voltage along with VPH1. At T3, when power switch 14 is turned on, VBOOT1 stops ringing and the voltage at VBOOT1 is initially equal to 2*VIN, but gradually decreases. With each successive cycle, the initial voltage of VBOOT1 is slightly lower than the previous cycle and continues to decline during the period in which power switch 14 is on. VBOOT1 continues to reduce each cycle until the boot cap 18 is eventually discharged and proper operation ceases.
FIG. 3 is a corresponding plot 44 of the output voltage VOUT1 during this same time. VOUT1 fails to regulate properly and continues to float higher until it eventually climbs to a value equal to VIN, about twice the desired regulated output voltage. However, if the load current is greater than a minimum value, then IL1 will not reduce to zero and the problems discussed above are avoided. For this reason, non-synchronous regulators are often limited to uses where there is a guaranteed minimum load. Synchronous regulators can be used in light load applications, however, synchronous regulators are often more expensive to produce.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to circuits and a method for providing a regulated output voltage at light or low loads from an unregulated input voltage, VIN. A switching power supply or switching regulator (e.g., non-synchronous buck converter) is provided with a control circuit (e.g., a pulse width modulator, FM modulator, hysteretic device, pulse skipping device, programmed modulator) that controls a control signal to a first switch. The input control signal is also coupled to a second switch in an inverted state, such as the first and second switches are switched xe2x80x9cONxe2x80x9d and xe2x80x9cOFFxe2x80x9d in opposing states. The first switch, referred to as the highside power switch or highside power FET, is coupled to a first voltage rail (e.g., an unregulated input voltage) and the second switch through a common node. The second switch, referred to as the lowside switch or lowside FET, is also coupled to a second voltage rail (e.g., ground). The highside switch is a power FET and the lowside switch is a weak FET. The lowside weak FET is designed to handle the small reverse current that occurs when the highside FET is turned off preventing the regulator from entering a discontinuous mode.
The method provides for turning the highside power switch and lowside switch in opposing xe2x80x9cONxe2x80x9d and xe2x80x9cOFFxe2x80x9d states. When the highside power switch switches xe2x80x9cONxe2x80x9d, the lowside switch switches to an xe2x80x9cOFFxe2x80x9d state. A charging current is provided through an inductor to charge an output capacitor. When the highside power switch switches xe2x80x9cOFFxe2x80x9d, the lowside switch switches to an xe2x80x9cONxe2x80x9d state clamping the common node of the highside power switch and the inductor to ground. An initial discharging current is provided by a diode coupled between ground and the common node, since the inductor does not want to reduce the charging current to zero instantaneously. The lowside switch provides a path for the reverse current of the inductor caused by a light load condition. When the lowside switch turns on, it clamps the voltage of the common node to ground and provides a path for the reverse current. This prevents the circuit from operating in the discontinues mode. An additional diode, when placed in series between the common node and the lowside switch can prevent substrate injection from the lowside switch which can occur when the highside power switch switches to an xe2x80x9cOFFxe2x80x9d state and the inductor pulls the common node below ground.
The following description and the annexed drawings set forth certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.